The present invention relates generally to the field of testing of integrated circuit devices and, more particularly, to a method of testing the programmable interconnect network in field programmable gate arrays.
A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks interconnected by a programmable routing network and programmable input/output cells. Programming of the logic blocks, the routing network and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application.
The present inventors have recently developed methods of built-in self-testing the array of programmable logic blocks and the programmable routing network in FPGAs at the device, board and system levels. These methods are set out in detail in U.S. Pat. Nos. 5,991,907; 6,003,150 and 6,202,182. The full disclosures in these patent applications are incorporated herein by reference.
In each of these prior methods, the reprogrammability of an FPGA is exploited so that the FPGA is configured exclusively with built-in self-test (BIST) logic during off-line testing and subsequently reconfigured to its normal operating configuration. In this way, testability at every level is achieved without overhead. In other words, the BIST logic simply xe2x80x9cdisappearsxe2x80x9d when the FPGA is reconfigured for its normal system function.
In addition to these off-line testing methods, the present inventors have also recently developed methods of on-line testing and fault tolerant operation of the programmable logic blocks of FPGAs. These methods are set out in detail in U.S. Pat. 6,256,758 and pending U.S. patent application Ser. No. 09/405,958. The full disclosure of this patent and patent application are also incorporated herein by reference.
On-line testing and fault tolerant operation of FPGAs is most important in high-reliability and high-availability applications, such as, space missions or telecommunication network routers in which adaptive computing systems often rely on reconfigurable hardware to adapt system operation. In such applications, the FPGA hardware must work continuously and simply cannot be taken off-line for testing, maintenance, or repair.
When faults are detected and located in the FPGA hardware of these systems, the FPGA resources must be quickly reconfigured to continue operation in a diminished capacity or to avoid the identified faulty resources altogether. Necessarily, therefore, testing of the FPGA resources must be performed concurrently with normal system operation.
In accordance with the present invention, the method of testing field programmable gate arrays (FPGAs) is carried out during normal on-line operation of the FPGA by configuring the FPGA resources into a working area and an initial self-testing area. The working area maintains normal operation of the FPGA under test throughout testing. Within the initial and subsequent self-testing areas, however, all the resources of the programmable routing network are tested. Advantageously, the working area is substantially unaffected by the testing, and testing time constraints are reduced since normal operation continues in the working area.
Within the self-testing areas test patterns are generated and propagated along groups of wires under test. The output patterns of a first group of wires under test are preferably compared to the output patterns of a second group of wires under test within the self-testing area receiving the same patterns. This method is similar to the BIST techniques described in detail in the above noted pending patent applications incorporated herein by reference.
In order to achieve a complete test of the programmable routing resources of the FPGA under test, the groups of wires under test include wire segments of varying lengths interconnected by configuration interconnect points. There are two basic types of configuration interconnect points, including cross-points and break-points, and each generally includes a transmission gate controlled by a configuration memory bit.
In addition, the groups of wires under test preferably include programmable logic blocks configured to allow the propagating test patterns to pass there through without alteration. In other words, the programmable logic blocks are configured as identity functions. Advantageously, this allows both global routing resources between programmable logic blocks and local routing resources leading to each programmable logic block to be tested.
As noted above, the output patterns of the groups of wires under test are compared and test result data is generated based on the outcome of the comparison. Passing test result data is generated if the corresponding test patterns match. If a mismatch occurs, a failing test result indication or data is generated. A failing test result or mismatch may be caused by a fault in a wire segment, a configuration interconnect point or a programmable logic block of the groups of wires under test in the self-testing area.
One limitation of this type of comparison-based response analysis is the potential for equivalent faults in the groups of wires under test. Equivalent faults along the groups of wires under test result in erroneous passing test results even though faults exist. In order to overcome this limitation, the preferred method of the present invention further includes the step of comparing the output of the first group of wires under test to the output of the second group of wires under test and the output of a third group of neighboring wires under test. This type of multiple testing substantially eliminates the potential for not detecting equivalent faults.
In order to minimize the number of reconfigurations of the FPGA under test and maintain a short total testing time, parallel testing of the programmable routing resources may be utilized. Specifically, comparisons of the output patterns of the groups of wires under test may be made at several locations along the groups of wires under test. Advantageously, one set of test patterns may be used to test several differing groups of wires per configuration. In addition, the test result data from several compared groups of wires under test may be combined utilizing an iterative comparator. Alternatively, the test result data can be routed directly to an input/output cell of the FPGA under test. Advantageously, this latter approach provides information regarding the location of the fault in the FPGA under test, as opposed to a single pass/fail test result indication for the entire test.
In accordance with an important aspect of the present invention, the self-testing area of the FPGA under test may be divided into vertical and horizontal self-testing areas. Preferably, vertical wire segments are tested utilizing the vertical self-testing area and horizontal wire segments are tested utilizing the horizontal self-testing area. To accommodate on-line testing, programmable logic blocks in both self-testing areas, vertical wire segments in the vertical self-testing area, and horizontal wire segments in the horizontal self-testing area are all designated reserved or unusable during operation of the FPGA under test. In this manner, connections between working area programmable logic blocks may be made utilizing horizontal wire segments through the vertical self-testing area and vertical wire segments through the horizontal self-testing area.
Upon completion of testing of the programmable routing resources located within the initial self-testing area, the FPGA under test is reconfigured so that a portion of the working area becomes a subsequent self-testing area, and the initial self-testing area becomes a portion of the working area. In other words, the self-testing area roves around the FPGA under test repeating the steps of reconfiguring and testing the programmable routing resources in the self-testing areas until each portion of the working area, or the entire FPGA, is reconfigured as a subsequent self-testing area and tested. As noted above, the present method of testing allows for normal operation of the FPGA under test to continue within the working area throughout testing, uninterrupted by the testing conducted within the self-testing areas.
The steps of configuring, testing, and reconfiguring the groups of wires under test and programmable logic blocks within the self-testing areas, storing the subsequent fault status data, and roving the self-testing area around the FPGA under test for further testing are necessarily controlled by a test and reconfiguration controller and an associated storage medium. In operation, the test and reconfiguration controller accesses the FPGA under test during normal system operation and configures the FPGA with one of a plurality of test configurations stored in the associated storage medium. As described above, test patterns generated within the self-testing area provide for exhaustive testing of the groups of wires under test. The test patterns are propagated along the groups of wires under test and the output patterns compared.